
PUBLICATIONS
Ongoing Papers
(In Prep)
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Geon Kim, Myoung Jin Lee, et al., “Analysis of current-fed push-pull converter using active-clamp method and voltage doubler”, IEEE Transactions on Power Electronics (SCI IF: 6.6) (in prep.)
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Jeonghyeon Yun, Myoung Jin Lee, et al., “Analysis of Fixed Charge Trap and Retention Time Improvement in Partial Isolation Buried Channel Array Transistor”, IEEE Transactions on Electron Devices (SCI IF: 2.9) (in prep.)
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Shinwook Kim, Myoung Jin Lee, et al., “Desing Point Optimization of Partial Isolation type LDMOS Using Reinforcement Learning”, IEEE Transactions on Electron Devices (SCI IF: 2.9) (in prep.)
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Juwon Lee, Myoung Jin Lee, et al., “Optimization of Partial Insulator in Buried Channel Array Transistor Dimensions for Enhancement of Electrical Properties Using Machine Learning”, IEEE Transactions on Electron Devices (SCI IF: 2.9) (in prep.)
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Chaehyuk Lim, Myoung Jin Lee, et al., “Gain cell embedded DRAM with Internal Amplification for High-Performance Applications”, IEEE Transactions on Circuits and Systems I (SCI IF: 5.2) (in prep.)
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Hyeona Seo, Myoung Jin Lee, et al., “Reduction of Device-to-Device Variability of 4H-SiC MOSFETs for Parallel Applications”, IEEE Transactions on Electron Devices (SCI IF: 2.9) (in prep.)
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Sowon Kim, Myoung Jin Lee, et al., “Analysis and Reduction of Single Event Upset (SEU) Effects on Row Hammer and GIDL in Buried Channel Array Transistors”, IEEE Transactions on Device and Materials Reliability (SCI IF: 2.5) (in prep.)
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Je Won Park, Myoung Jin Lee, et al., “Exploring Total Ionizing Dose Effects in Enclosed Layout Transistors: Insights from Experimental Characterization and Advanced Simulations”, IEEE Transactions on Device and Materials Reliability (SCI IF: 2.5) (in prep.)
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Suyeon Kim, Myoung Jin Lee, et al., “An Improved DRAM Design with Reduced Temperature and Cell-to-Cell Interference Effects”,IEEE Transactions on Electron Devices (SCI IF: 2.9) (in prep.)
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Dongyeong Kim, Myoung Jin Lee, et al., “Bayesian Sequential Sampling for Yield Estimation and Statistical Optimization of DRAM Sense Amplifiers”, IEEE Transactions on Circuits and Systems I (SCI IF: 5.2) (in prep.)
(In Review)
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Geon Kim, Myoung Jin Lee, et al., “High-Efficiency Boosting with Interleaved and Active-Clamp Converter Topologies for Fuel Cell-Based Renewable Energy Systems”, Chemical Engineering Journal (SCI IF: 13.4) (in review.)
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Hyerin Lee, Myoung Jin Lee, et al., “Machine Learning–based Uncertainty Quantification and Design Optimization for Offset-Compensation Sense Amplifiers in DRAMs”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, submitted. Feb. 2025 (SCI IF: 2.7) (in review.)
Peer Reviewed Journals (2024-Current)
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Shinwook Kim, Myoung Jin Lee, et al., “Enhancing Design Stability and Flexibility in Partial Isolation type LDMOS”, IEEE Access, vol.13, pp. 40090-40102, Mar. 2025 (SCI IF: 3.4)
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Dongyeong Kim, Myoung Jin Lee, et al., “Model-Based Variation-Aware Optimization for Offset Calibration and Pre-Sensing in DRAM Sense Amplifiers”, IEEE Access, vol. 13, pp. 14165-14176, Jan. 2025 (SCI IF: 3.4)
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Je Won Park, Myoung Jin Lee, et al., “Enhancing Total-Ionizing-Dose Effects in the Partial Insulator in a Buried-Channel-Array Transistor: A Structural Proposal and Analytical Approach,” IEEE Transactions on Device and Materials Reliability, accepted, Nov. 2024 (SCI IF: 2.5)
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Eojin Kim, Myoung Jin Lee, et al., “Addition of carbon dioxide enhances electrical power production in a microbial reverse electrodialysis cell,” Journal of Water Process Engineering, vol. 68, pp. 1-10, Nov. 2024 (SCI IF: 6.7)
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Suyeon Kim, Myoung Jin Lee, et al., “Passing Word Line-induced Subthreshold Leakage Reduction Using a Partial Insulator in a Buried Channel Array Transistor”, IEEE Transactions on Electron Devices, vol. 71, no. 5, pp. 2976-2982, May. 2024 (SCI IF: 2.9)
Peer Reviewed Journals (2020-2023)
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Junyeoung Bae, Myoung Jin Lee, et al., “Timestamp-Based Secure Shield Architecture for Detecting Invasive Attacks” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 31, no. 9, pp. 1358-1367, Sept. 2023 (SCI IF: 2.8)
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Jin Hyo Park, Myoung Jin Lee, et al., “Row Hammer Reduction Using a Buried Insulator in a Buried Channel Array Transistor” in IEEE Transactions on Electron Devices, vol. 69, no. 12, pp. 6710-6716, Dec. 2022 (SCI IF: 3.1)
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Geon Kim, Myoung Jin Lee, et al., “4-Pole Hybrid HVDC Circuit Breaker For Pole-to-pole(PTP) Fault Protection”, IEEE Access, vol. 10, pp. 39789-39799, April. 2022 (SCI IF: 3.367)
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Seonwoo Jung, Myoung Jin Lee, et al., “Predicting Ischemic Stroke in Patients with Atrial Fibrillation Using Machine Learning” Front Biosci (Landmark Ed). 2022 Mar 4;27(3) (SCI IF: 4.009)
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Jin Hyo Park, Myoung Jin Lee, et al., “S-TAT Leakage Current in Partial Isolation Type Saddle-FinFET (Pi-FinFET)s”, IEEE Access, vol. 9, pp. 111567-111575, Aug. 2021 (SCI IF: 3.367)
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Geon Kim, Myoung Jin Lee, et al., “A Zero Crossing Hybrid Bidirectional DC Circuit Breaker for HVDC Transmission Systems”, Energies, Mar. 2021, 14, 1349 (SCI IF: 2.702)
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Jin-sung Lee, Myoung Jin Lee, et al., “Partial Isolation Type Buried Channel Array Transistor (Pi-BCAT) for a Sub-20 nm DRAM Cell Transistor”, Electronics, Nov. 2020, 9, 1908 (SCI IF: 2.11)
Peer Reviewed Journals (2016-2019)
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Young Kwon Kim, Myoung Jin Lee, et al., “Partial Isolation Type Saddle-FinFET(Pi-FinFET) for Sub-30 nm DRAM Cell Transistors”, Electronics Dec. 2018, 8, 8 (SCI IF: 2.11)
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Young Kwon Kim, Myoung Jin Lee, et al., “Simulation Analysis in Sub-0.1um for Partial Isolation Field-Effect Transistors”, Electronics, Oct. 2018, 7(10), 227. (SCI IF: 2.11)
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Young Kwon Kim, Myoung Jin Lee, et al., “FN-tunneling-current Modeling in a Recessed-channel Structure”, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, vol.17, no.5, Oct. 2017, pp709~716. (SCI IF: 0.766)
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Young Kwon Kim, Myoung Jin Lee, et al., “The Optimized Partial Insulator Isolation MOSFET(PiFET)”, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, vol.17, no.5, Oct. 2017, pp729~732. (SCI IF: 0.766)
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HuiJung Kim, Myoung Jin Lee, et al., "Near Infrared Detection Using Pulsed Tunneling Junction in Silicon Devices“, IEEE Transactions on electron devices, vol. 63, no. 1, pp. 377-383, Jan. 2016 (SCI IF: 2.62)
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HuiJung Kim, Myoung Jin Lee, et al., "An analysis of a Modified Recessed Active Tunneling Field Effect-Transistor“, Japanese Journal of Applied Physics 55, 074201, June. 2016. (SCI IF: 1.452)
Peer Reviewed Journals (-2015)
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Myoung Jin Lee, "A sensing noise compensation Bit Line Sense Amplifier for low voltage applications", IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 3. Mar. 2011 (SCI IF: 4.075)
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Myoung Jin Lee, Kun Woo Park, et al., "A Selective Negative Word Line Scheme for improving refresh", IEE Electronics Letters, vol. 47, issue 3. Feb. 2011 (SCI IF: 1.232)
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Myoung Jin Lee, Kun Woo Park, "A Mechanism for Asymmetric Data Writing Failure", Solid-State Electronics, vol. 56, pp.211~213. Feb. 2011 (SCI IF: 1.666)
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Myoung Jin Lee, Kun Woo Park, "A Mechanism for Dependence of Refresh Time on Data Pattern in DRAM", IEEE ELECTRON DEVICE LETTERS / VOL. 31, NO. 2 / pp. 168-170. Feb. 2010 (SCI IF: 3.433)
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Myoung Jin Lee, Chang-Ki Baek, et al., "A comparative study of the DRAM leakage mechanism for planar and recessed channel MOSFETs", Solid-State Electronics / vol. 53, issue. 9 / pp. 998~1000. Sep. 2009 (SCI IF: 1.666)
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Myoung Jin Lee, Seonghoon Jin, et al., "A Proposal on an Optimized Device Structure with Experimental Studies on Recent Devices for the DRAM Cell Transistor", IEEE Transactions on electron devices / VOL. 54, NO. 12 / pp. 3325~3335. Dec. 2007 (SCI IF: 2.62)
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Seonghoon Jin, Myoung Jin Lee, et al., "A New Direct Evaluation Method to Obtain the Data Retention Time Distribution of DRAM", IEEE Transactions on electron devices / VOL. 53, NO. 9 / pp. 2344-2350. Sept. 2006 (SCI IF: 2.62)
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Myoung Jin Lee, Jun Hee Cho, et al., "Partial SOI Type Isolation for Improvement of DRAM Cell Transistor Characteristics", IEEE ELECTRON DEVICE LETTERS / VOL. 26, NO. 5 / pp. 332-334. May. 2005 (SCI IF: 3.433)
International Conferences
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Hyerin Lee, Myoung Jin Lee, "Machine Learning based Design Approach for Optimizing DRAM Sense Amplifier", International Conference on Electronics, Information, and Communication (ICEIC) 2025
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Shinwook Kim, Myoung Jin Lee, "Gate Recess Structure Optimization for Normally-off state GaN HEMTs", International Conference on Electronics, Information, and Communication (ICEIC) 2025
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Chaehyuk Lim, Myoung Jin Lee, "Data Retention Characteristics of GC-eDRAM under PVT variations", International Conference on Electronics, Information, and Communication (ICEIC) 2025
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Hyeona Seo, Myoung Jin Lee, "Enhanced Electrical Performance and Reliability of 1.2kV 4H-SiC MOSFET With P-well Design", International Conference on Electronics, Information, and Communication (ICEIC) 2025
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Jeong Hyeon Yoon, Myoung Jin Lee, "Temperature-Resistant DRAM Solutions: Pi-BCAT Structure for Minimizing Leakage Current", International Conference on Electronics, Information, and Communication (ICEIC) 2025
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Juwon Lee, Myoung Jin Lee, "Machine Learning for DRAM Pi-BCAT Enhancement", International Conference on Electronics, Information, and Communication (ICEIC) 2025
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Sowon Kim, Myoung Jin Lee, "Analysis of the Influence of SEU by Heavy Ion Incident Angle in MOSFET", International Conference on Electronics, Information, and Communication (ICEIC) 2025
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Suyeon Kim, Myoung Jin Lee, "BCAT Leakage Prediction Using Linear Regression", International Conference on Electronics, Information, and Communication (ICEIC) 2025
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Dongyeong Kim, Myoung Jin Lee, "Design and Optimization of a Low-Voltage DRAM Sense Amplifier With Hybrid Offset Calibration Technique", International Conference on Electronics, Information, and Communication (ICEIC) 2025
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Je Won Park, Myoung Jin Lee, "Variations in the GIDL Region of Partial Insulator in a Buried-Channel-Array Transistor Induced by Total Ionizing Dose Effects", International Conference on Electronics, Information, and Communication (ICEIC) 2025
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Jin Hong Ahan, Myoung Jin Lee, “A Double-Side CMOS-CNT Biosensor Array with Padless Structure for Simple Bare-Die Measurements in a Medical Environment”, 2015 IEEE International Solid-State Circuits Conference
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Myoung Jin Lee, Ki Myoung Kyoung, "A Bitline Sense Amplifier for Offset Compensation", 2010 IEEE International Solid-State Circuits Conference, 24.4, pp. 438-439.
Domestic Journals
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Dongyeong Kim, Myoung Jin Lee, et al., "구동라인 분리 센스앰프의 딜레이 페일 개선 효과에 대한 분석”, 한국전기전자학회 한국전기전자학회논문지 / VOL. 28, NO. 1 / pp. 1~5. Mar. 2024
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Suyeon Kim, Myoung Jin Lee, et al., “BCAT구조 DRAM의 패싱 워드 라인 유도 누설전류 분석”, 한국전기전자학회 한국전기전자학회논문지 / VOL. 27, NO. 4 / pp. 277~282. Jan. 2024
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Shinwook Kim, Myoung Jin Lee, “Partial-isolation LDMOS의 항복전압과 온저항 분석”, 한국전기전자학회 한국전기전자학회논문지 / VOL. 27, NO. 4 / pp. 200~205. Jan. 2024
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Je Won Park, Myoung Jin Lee, “부분분리 매립 채널 어레이 트랜지스터의 총 이온화 선량 영향에 따른 특성 해석 시뮬레이션”, 한국전기전자학회 한국전기전자학회논문지 / VOL. 27, NO. 3 / pp. 303~307. Sept. 2023
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Dongyeong Kim, Myoung Jin Lee, et al., “전압 래치 센스앰프의 오프셋 감소 기법”, 대한전자공학회 전자공학회논문지 / VOL. 59, NO. 6 / pp. 32~35. June. 2022
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Hong-Ryeol Yang, Myoung Jin Lee, et al., “Design of a LiDAR sensor to help AGVs avoid obstacles”, 한국디지털콘텐츠학회 디지털콘텐츠학회논문지 / VOL. 22, NO. 5 / pp. 877~888. May. 2021
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Myoung Jin Lee, “신뢰성 개선된 IGBT 소자 신구조”, 한국디지털콘텐츠학회 디지털콘텐츠학회논문지 / VOL. 18, NO. 6 / pp. 1193~1198. Oct. 2017
Domestic Conferences
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Suyeon Kim, Myoung Jin Lee, et al., "Mitigating Subthreshold Leakage in DRAM: A Comparative Study of BCAT and PI-BCAT Structures under Thermal Stress", 제 32회 한국반도체학술대회 논문집 / 25.02.13
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Je Won Park, Myoung Jin Lee, et al., "Enhancement of TID Resistance through Aluminum Shielding", 제 32회 한국반도체학술대회 논문집 / 25.02.13
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Shinwook Kim, Myoung Jin Lee, et al., "Gate Recessed Structure Analysis for Normally-off state GaN HEMTs", 제 32회 한국반도체학술대회 논문집 / 25.02.13
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Juwon Lee, Myoung Jin Lee, et al., "DRAM Pi-BCAT Structure Using Machine Learning", 제 32회 한국반도체학술대회 논문집 / 25.02.13
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Dongyeong Kim, Myoung Jin Lee, "Analytical Model for Diode Connection-Based DRAM Sense Amplifier Margin Enhancement", 2024 IEEE Seoul Section Student Paper Contest / 24.12.07
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Suyeon Kim, Myoung Jin Lee, "Mitigation of Passing Word Line Coupling-Induced Row Hammering Effect in 6F² DRAM Layouts Using Pi-BCAT Structure", 2024 IEEE Seoul Section Student Paper Contest / 24.12.07
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Je Won Park, Myoung Jin Lee, "Analysis of Total Ionizing Dose Effects Based on the Thickness of the STI Region in Buried Channel Array Transistors", 2024 IEEE Seoul Section Student Paper Contest / 24.12.07
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Juwon Lee, Myoung Jin Lee, "머신러닝을 이용한 DRAM Pi-BCAT구조", 2024년 한국전기전자학회 하계학술대회 논문집 / 24.08.13
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Hyerin Lee, Myoung Jin Lee, et al., "DRAM Sense Amplifier의 Sensing Time 예측을 위한 머신러닝 알고리즘 성능 비교평가", 2024년 한국전기전자학회 하계학술대회 논문집 / 24.08.13
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Hyeona Seo, Myoung Jin Lee, et al., "스위칭 손실 저감을 위한 1.2kV SiC MOSFET의 JFET 영역 조정", 2024년 한국전기전자학회 하계학술대회 논문집 / 24.08.13
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Sowon Kim, Myoung Jin Lee, et al., "Heavy ion 입사 각도에 따른 MOSFET 특성 분석", 2024년 한국전기전자학회 하계학술대회 논문집 / 24.08.13
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Chaehyuk Lim, Myoung Jin Lee, et al., "eDRAM cell 구조에 따른 retention time 분석", 2024년 한국전기전자학회 하계학술대회 논문집 / 24.08.13
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Jeong Hyeon Yoon, Myoung Jin Lee, et al., "머신러닝을 이용한 DRAM 누설전류 예측", 2024년 한국전기전자학회 하계학술대회 논문집 / 24.08.13
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Shinwook Kim, Myoung Jin Lee, et al., "Pi-LDMOS의 partial insulator aspect ratio 분석", 2024년 한국전기전자학회 하계학술대회 논문집 / 24.08.13
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Je Won Park, Myoung Jin Lee, et al., "Total Ionizing Dose 노출에 따른 Gate-Induced Drain Leakage 영역 Variations 분석", 2024년 한국전기전자학회 하계학술대회 논문집 / 24.08.13
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Suyeon Kim, Myoung Jin Lee, et al., "BCAT과 Pi-BCAT구조의 온도에 따른 DRAM문턱이하 누설전류 증가", 2024년 한국전기전자학회 하계학술대회 논문집 / 24.08.13
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Dongyeong Kim, Myoung Jin Lee, et al., "DRAM 오프센 캔슬링 센스앰프 타입에 따른 센싱마진 개선 효과 분석", 2024년 한국전기전자학회 하계학술대회 논문집 /24.08.13
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Suyeon Kim, Myoung Jin Lee, et al., "Passing Word Line Induced Subthreshold Leakage Reduction by a Partial Insulator in a Buried Channel Array Transistor", 제 31회 한국반도체학술대회 논문집 / 24.01.26
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Je Won Park, Myoung Jin Lee, et al., "Row Hammer Characteristics by Total Ionization Dose Effect (TID) in Partial Isolation Type Buried Channel Array Transistor (Pi-BCAT)", 제 31회 한국반도체학술대회 논문집 / 24.01.26
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Shinwook Kim, Myoung Jin Lee, et al., "Breakdown Voltage Improvement in Junction Isolation Type LDMOS", 제 31회 한국반도체학술대회 논문집 / 24.01.26
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Dongyeong Kim, Myoung Jin Lee, et al., "기판 바이어스 및 과구동 전압 활용 CMOS 인버터 특성 개선 기법", 제 31회 한국반도체학술대회 논문집 / 24.01.26
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Hyeona Seo, Myoung Jin Lee, et al., "CMOS Gate Length 감소에 따른 Short Channel Effect 심화와 성능 파라미터 변화 분석", 2023년 한국전기전자학회 하계학술대회 논문집 / 23.08.17
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Juwon Lee, Myoung Jin Lee, et al., " CLSA, VLSA의 width size 변화에 따른 센스앰프 동작속도에 대한 분석", 2023년 한국전기전자학회 하계학술대회 논문집 / 23.08.17
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Chaehyuk Lim, Myoung Jin Lee, et al., "Buried Channel Array Transistor의 파라미터 변화에 따른 Radiation 누설전류", 2023년 한국전기전자학회 하계학술대회 논문집 / 23.08.17
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Sowon Kim, Myoung Jin Lee, et al., "PiFET의 측면 산화물의 변화에 따른 트랜스컨덕턴스 분석", 2023년 한국전기전자학회 하계학술대회 논문집 / 23.08.17
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Suyeon Kim, Myoung Jin Lee, et al., "Subthreshold leakage in Buried Channel Array Transistor", 2023년 한국전기전자학회 하계학술대회 논문집 / 23.08.17
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Dongyeong Kim, Myoung Jin Lee, et al., "Improvement of CMOS Inverter Characteristics using Over-driving and Substrate Bias", 2023년 한국전기전자학회 하계학술대회 논문집 / 23.08.17
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Shinwook Kim, Myoung Jin Lee, et al., "RF적용을 위한 부분 절연 전계 효과 트랜지스터", 2023년 한국전기전자학회 하계학술대회 논문집 / 23.08.17
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Je Won Park, Myoung Jin Lee, et al., "Characteristics by Total Ionizing Dose Effects in Partial Isolation Buried Channel Array Transistor", 2023년 한국전기전자학회 하계학술대회 논문집 / 23.08.17
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Suyeon Kim, Myoung Jin Lee, et al., "Partial Isolation Type Buried Channel Array Transistor (Pi- BCAT)에서 Passing Gate의 영향에 대한 문턱전압과 누설전류 분석", 제 30회 한국반도체학술대회 논문집 / 23.02.15
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Dongyeong Kim, Myoung Jin Lee, et al., "Separated Driving-node Sense Amplifier with Enhanced Sensing Margin for Low Voltage Applications", 제 30회 한국반도체학술대회 논문집 / 23.02.15
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Suyeon Kim, Myoung Jin Lee, et al., "Passing Gate Reduction by a Partial Insulator in a Buried Channel Array Transistor", 2022 IEEE Seoul Section Student Paper Contest / 22.12.17
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Dongyeong Kim, Myoung Jin Lee, et al., "Bit-line Sense Amplifier with Sensing Offset", 2022 IEEE Seoul Section Student Paper Contest / 22.12.17